Conventional testing of the interconnect wiring levels of integrated circuits requires three separate reliability tests to be performed, time dependent dielectric breakdown, electromigration and stress migration as using independent structures and tests. However, in real integrated circuit operation, the mechanisms that cause time dependent dielectric breakdown, electromigration and stress migration can interact. Not only do conventional testing methods not account for these interactions, but are wasteful of time and test resources as the first failure time from one of those three mechanisms determines the entire chip reliability. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.